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1. Technical Field
This invention is in the field of semiconductor integrated circuit random access memory devices and, more specifically, is directed to xe2x80x9chidingxe2x80x9d refresh operations of a DRAM array to faithfully emulate an SRAM-type interface.
2. Background of the Invention
In an asynchronous SRAM, there are generally three modes of operation: read, write, and standby. In read mode, a change of input address signals the start of a read operation. Sufficient time, referred to as xe2x80x9cread cycle time,xe2x80x9d must be allowed after the change of address for the read operation to complete. If the time allowed is less than the minimum read cycle time, the read operation is aborted, known as an invalid read. The consequences of an invalid read are that the output data is invalid, but the content of the memory is unaffected. Write operations are triggered by the assertion (typically active low) of external signals W# (write-complement or xe2x80x9cwrite-barxe2x80x9d) or CS# (chip select-complement or xe2x80x9cCS-barxe2x80x9d). Write operations that last for less than a predetermined xe2x80x9cwrite cycle timexe2x80x9d are not allowed.
Accessing and refreshing DRAM arrays is a different matter. Unlike SRAM cells, reading of a DRAM cell is destructive, as it discharges the selected storage capacitors. After each read operation, therefore, the sensing amplifier has to write the data back to the cell to restore the cell content. Every read operation must be completed in this fashion or else cell contents will be lost. In contrast, an SRAM read operation can be aborted at any time without destroying cell content.
DRAM cells also need to be refreshed periodically due to storage cell leakage. A refresh operation is a dummy read operation, where the cell is read and its data written back. If a cell is not refreshed for a specified period of time (refresh interval), it will lose its data content. A typical refresh interval at this writing is on the order of 64 milliseconds. Static RAM (SRAM) has no refresh requirement but is relatively large (less dense) and consumes more power than DRAM per bit.
Various DRAM and SRAM designs are known in the art. A number of attempts have been made to make DRAM appear to work like SRAM, but these efforts have been only partially successful. One example is disclosed in Leung et al. U.S. Pat. No. 5,999,474 for xe2x80x9cMethod and apparatus for complete hiding of the refresh of a semiconductor memory.xe2x80x9d The apparatus includes a multi-bank DRAM memory and an SRAM cache that stores the most recently accessed data. Each access is stored in the SRAM cache. When there is a cache hit, the DRAM bank is not accessed, allowing time for the DRAM bank to be refreshed. The size of the SRAM cache is determined to guarantee sufficient refresh rate. This method, however, due to its complexity, can only be implemented in a synchronous design, where an external clock is present. It would be extremely difficult or impossible to implement this method in asynchronous design.
xe2x80x9cUtRAMxe2x80x9d (Unit transistor RAM) is produced by Samsung Electronics Co., Ltd. The product datasheet (part # K5Q6432YCM-T010) indicates that it uses a DRAM memory core, with refresh hidden from the external interface. The interface is similar to that of an asynchronous SRAM, but still clearly incompatible with asynchronous SRAM. The datasheet documents two flaws that make it incompatible with SRAM, namely:
1. When invalid read operations occur continuously, the internal refresh operations cannot be performed, resulting in data loss.
2. When write operations occur continuously, the internal refresh operations cannot be performed, resulting in data loss.
The implementation details of xe2x80x9cUtRAMxe2x80x9d have not been disclosed publicly. In any event, the product does not completely xe2x80x9chidexe2x80x9d refresh from the external interface as noted above. In other words, Samsung UtRAM imposes timing restrictions on the external interface beyond the usual SRAM requirements. Consequently, the UtRAM and similar products cannot provide a fully pin-compatible substitute in an SRAM-interface application.
Fujitsu offers a product called xe2x80x9cFCRAMxe2x80x9d (Fast-Cycle RAM)xe2x80x94a pipelined DRAM core design. Its interface resembles that of asynchronous SRAM. However, it appears from the published datasheet that FCRAM operates differently from asynchronous SRAM. For example, an asynchronous SRAM can start a read cycle with an address change. FCRAM, however, requires explicitly triggering each read cycle with CS# or OE signals. FCRAM also imposes timing requirements for write operations that differ significantly from those of conventional asynchronous SRAM.
Thus, the need remains for a memory device that completely hides refresh operations, and provides a pin-compatible substitute for conventional SRAM along with improved density and lower power requirements.
The present invention includes improved methods, circuits and products that are especially useful to implement pin-compatible substitutes for conventional SRAM. One aspect of the invention is a novel refresh strategy that is completely hidden from the user interface; it imposes no special restrictions on access timing and the like. Rather, a semiconductor memory product that implements the new refresh strategy can be made to present an external interface that behaves just like conventional (asynchronous) SRAM. The user (or systems in which such a memory is deployed) can ignore refresh entirely; it is invisible. However, because the improved memory products leverage DRAM memory cells internally, they provide substantially greater density, and lower power consumption, than SRAM products.
The new refresh method is based on prohibiting the start of a refresh operation during certain periods (i.e., under certain conditions), but otherwise continuously refreshing the array, rather than affirmatively scheduling refresh at certain times as in the prior art. In particular, refresh operations are ongoing continuously, driven by an internal clock that generates periodic refresh requests, except during specific periods when a read or write operation is actually accessing the memory array. In other words, the new scheme executes a refresh at any time (i.e., whenever requested by a refresh generator), except during selected periods when the start of a refresh operation is prohibited. In this regard the refresh operates asynchronously. More specifically, according to the present invention, a period or xe2x80x9ctime slotxe2x80x9d in which to complete a pending refresh operation is inserted within every read and every write cycle. In prior art, refresh is scheduled during periods when read and write accesses are prohibited. Thus, the present invention is characterized by essentially interleaving (external) memory accesses and refresh operations, rather than temporally segregating them as in prior art. This feature has the benefit of alleviating interface restrictions that characterize the prior art such as those described above.
According to another aspect of the invention, a single refresh operation refreshes only a limited number of rows of the memory array, specifically one row in a presently preferred embodiment, whereas the prior art xe2x80x9cauto refreshxe2x80x9d cycle refreshes the entire array. The new, one-row refresh is fast; time to complete an individual row refresh is inserted during every access by xe2x80x9cstretchingxe2x80x9d the read or write cycle. (A particular time slot may not actually be used to complete a refreshxe2x80x94as further explained laterxe2x80x94but it is made available.) Note that a time to complete the pending refresh is provided because, as alluded to above, a refresh starts to execute immediately upon request, except during certain xe2x80x9crefresh start prohibitedxe2x80x9d periods. The start of a refresh operation is prohibited only when a pending read/write array access must be completed. Otherwise, a refresh operation generally begins when initiated by the refresh circuit, and time to complete the refresh is always available by virtue of the xe2x80x9cstretchedxe2x80x9d read and write cycles.
Another aspect of the invention calls for isolating the internal memory array from the data input/output (I/O) structures such as buffers and pins. In one presently preferred embodiment, this isolation is implemented using a latch (or latching register) between the sense amplifiers and the I/O structures. This enables segregating the array access (or simply xe2x80x9caccessxe2x80x9d) time from the data I/O portions of a memory operation. A data input (sometimes called xe2x80x9cdatainxe2x80x9d) operation or a data output operation (dataout), preceding a data write access or following a data read access, respectively, does not interfere with completion of a refresh access operation once the I/O structures are segregated from the array.
The method provided by this invention can be implemented asynchronously. As a result, a low-power asynchronous SRAM substitute device can be built using DRAM cells. Asynchronous SRAM, compared to its synchronous counterpart, consumes much lower power because it does not need a clock. DRAM cells provide power savings as well, and vastly higher density over SRAM.
Additional objects and advantages of this invention will be apparent from the following detailed description of preferred embodiments thereof which proceeds with reference to the accompanying drawings.